A Novel Instruction Set for the Packet Processing on the Network ASIP

In this paper, we propose a new instruction set for a network ASIP(Application Specific Instruction-set Processor). The new instruction set was designed for the packet processing engine on a network router. The network ASIP to accelerate the packet processing operation was built on a baseline ASIP, which is based on the general RISC structure. The new instruction set is divided into two groups. They are operated on each of its functional unit within the execution stage. After the derivation of the HDLmodel from LISA, the functional units were replaced by a hand-written Verilog-HDL.